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THC63LVD1024_rev.2.4_e copyright?2012 thine electronics, inc. 1/23 thine electronics, inc. THC63LVD1024 135mhz 67bits lvds receiver general description the THC63LVD1024 receiver is designed to support dual link transmission between host and flat panel display up to 1080p/qxga resolutions. the THC63LVD1024 converts th e lvds data streams back into 67bits of cmos/ttl data with falling edge or ris- ing edge clock for convenie nt with a variety of lcd panel controllers. in dual link, data tr ansmit clock frequency of 135mhz, 67bits of rgb data are transmitted at an effective rate of 945mbps per lvds channel. using a 135mhz clock, the data throughput is 1.1gbytes per second. features ? wide dot clock range suited for tv signal(480i- 1080p), pc signal(vga-qxga) dual lvds port in/dual ttl port out mode: 8 - 135mhz(clkout) dual lvds port in/single ttl port out mode: 40 - 150mhz(clkout) ? pll requires no external components ? flexible input/output mode 1. single/dual lvds port in /single/dual ttl port out 2. double edge output ? 50% output clock duty cycle ? ttl clock edge selectable ? ttl clock output timing programmable(3 step) ? 2 output data mapping for simplifying pcb layout. ? power down mode ? low power single 3.3v cmos design ? 144pin lqfp exposed pad block diagram serial to parallel pll 35 35 ra1 +/- rb1 +/- rc1 +/- rd1 +/- mode[2:0] /pdwn rclk +/- (8 to 135mhz) lvds input 32 r1[9:0] receiver clock out (8 to 150mhz) ttl output lvds input re1 +/- ra2 +/- rb2 +/- rc2 +/- rd2 +/- re2 +/- port1 lvds input port2 dk g1[9:0] b1[9:0] cont1[2:1] port1 o/e serial to parallel data formatter 1) demux 3) ddr 2) mux r/f map 32 r2[9:0] ttl output g2[9:0] b2[9:0] cont2[2:1] port2 3 hsync vsync de
THC63LVD1024_rev.2.4_e copyright?2012 thine electronics, inc. 2/23 thine electronics, inc. pin out 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 vcc cont12 vsync de cont11 vcc r27 oe map mode1 mode0 mode2 reserved dk /pdwn r20 pvcc pgnd b17 b16 b15 b11 gnd b14 b13 b12 vcc b10 g19 g18 g17 g16 g15 gnd vcc g14 g13 g12 g11 g10 r19 r17 r16 gnd vcc r15 r14 r13 r12 r10 pgnd pvcc vcc b19 hsync gnd gnd r21 r22 r23 r24 r25 r26 vcc r28 r29 g20 vcc gnd g21 vcc g22 g23 g24 g25 g26 g27 g28 g29 vcc gnd b20 b21 b22 b23 b24 b25 r11 r/f b26 b27 b28 b29 vcc gnd vcc cont22 cont21 clkout gnd gnd vcc gnd cvcc cgnd r18 b18 gnd lgnd re2+ re2- rd2+ rd2- lgnd lgnd rc2+ rc2- lgnd lvcc rb2+ rb2- ra2+ ra2- lgnd lgnd lgnd lgnd lgnd re1+ re1- rd1+ rd1- rc1+ rc1- rclk+ rclk- rb1+ rb1- ra1- ra1+ lvcc lvcc lvcc lvcc tssop144 exposed pad top view 145gnd(exposed pad)
THC63LVD1024_rev.2.4_e copyright?2012 thine electronics, inc. 3/23 thine electronics, inc. pin description pin name pin # type description ra1+, ra1- 111, 110 lvds in the 1st link. the 1st pixel input data when dual link. rb1+, rb1- 113, 112 lvds in rc1+, rc1- 117, 116 lvds in rd1+, rd1- 123, 122 lvds in re1+, re1- 125, 124 lvds in rclk+, rclk- 119, 118 lvds in lvds clock input. ra2+, ra2- 129, 128 lvds in the 2nd link. these pins are disabled when single link. rb2+, rb2- 131, 130 lvds in rc2+, rc2- 135, 134 lvds in rd2+, rd2- 141, 140 lvds in re2+, re2- 143, 142 lvds in r19 ~ r10 74 - 72, 69 - 63 out the 1st pixel data outputs. g19 ~ g10 86 - 82, 79 - 75 out b19 ~ b10 100, 99, 96-90, 87 out r29 ~ r20 25-23, 20-14 out the 2nd pixel data outputs. g29 ~ g20 40, 37 - 31, 27, 26 out b29 ~ b20 52 - 48, 45 - 41 out cont11,cont12 104, 105 out user defined data output cont21,cont22 55, 56 de 103 out data enable output. vsync 102 out vsync output. hsync 101 out hsync output. clkout 60 out clock output. /pdwn 4 in power down and outp ut control.(table1) h: normal operation l: power down mode1, mode0 6, 5 in pixel data mode . mode1 mode0 mode h h single link (single-in/single-out) h l single link (single-in/dual-out) l h dual link (dual-in/single-out) l l dual link (dual-in/dual-out)
THC63LVD1024_rev.2.4_e copyright?2012 thine electronics, inc. 4/23 thine electronics, inc. dk 7 in output clock delay timing select. r/f 8 in output clock triggering edge select. h: rising edge, l: falling edge. oe 9 in output enable.(table1) h: output enable, l: output disable mode2 10 in ddr function enable. the use of this function depends on the setting of mode<1:0>. mode<1:0>=lh(dual-in/single-out mode) h: ddr (double edge output) function enable. l: ddr (double edge output) function disable. mode<1:0>=other must be tied to gnd map 11 in lvds mapping table select. see fig9,10 and table2 - 9. h: mapping mode1 l: mapping mode2 reserved 3 in must be tied to vcc. vcc 12, 21, 28, 29, 38, 46, 53, 57, 70, 80, 88, 97, 106 power power supply pins for ttl outputs and digital circuitry. gnd 13, 22, 30, 39, 47, 54, 58, 59, 71, 81, 89, 98,145 ground ground pins for ttl outputs and digital circuitry. lvcc 114, 120, 126, 132, 138 power power supply pins for lvds inputs. lgnd 109, 115, 121, 127, 133, 136, 137, 139, 144 ground ground pins for lvds inputs. pvcc 2, 107 power power supply pin for pll circuitry. pgnd 1, 108 ground ground pin for pll circuitry. cvcc 61 power power supply pins for ttl output of clkout. cgnd 62 ground ground pins for ttl output of clkout pin name pin # type description t dout =output data cycle mode[1:0 ] dk offset [nsec] ll hh hl l0 m h lh l0 m h 6 t dout 28 -------------- - ? 6 t dout 28 -------------- - 7 t dout 28 -------------- - ? 7 t dout 28 -------------- - pin description (continued)
THC63LVD1024_rev.2.4_e copyright?2012 thine electronics, inc. 5/23 thine electronics, inc. pin description (continued) table 1. output control absolute maximum ratings pd oe data outputs (rxn) clkout l l hi-z hi-z l h all low fixed low h l hi-z hi-z h h data out clk out supply voltage (v cc ) -0.3v ~ +4.0v cmos/ttl input voltage -0.3v ~ (v cc + 0.3v) cmos/ttl output voltage -0.3v ~ (v cc + 0.3v) lvds receiver input voltage -0.3v ~ (v cc + 0.3v) output current -30ma ~ 30ma junction temperature +125 storage temperature range -55 ~ +125 reflow peak temperature / time +260 / 10sec. maximum power dissipation @+25 4.4w c c c c c
THC63LVD1024_rev.2.4_e copyright?2012 thine electronics, inc. 6/23 thine electronics, inc. recommended oper ating conditions parameter min. typ max units all supply voltage 3.0 3.3 3.6 v operating ambient temperature 0 70 clk frequency mode<1:0>=ll dual-in/dual-out lvds input 8 135 mhz output 8 135 mhz mode<1:0>=lh dual-in/single-out single edge output (mode2=l) lvds input 20 75 mhz output 40 150 mhz double edge output (mode2=h) lvds input 20 75 mhz output 20 75 mhz mode<1:0>=hl single-in/dual-out lvds input 8 135 mhz output 4 67.5 mhz mode<1:0>=hh single-in/single-out lvds input 8 135 mhz output 8 135 mhz differential clkin high time ( t rcih ) (fig1) nsec differential clkin low time ( t rcil ) (fig1) nsec c 2 t rcip 7 ----------------- 5 t rcip 7 ----------------- 2 t rcip 7 ----------------- 5 t rcip 7 ----------------- v diff = 0v v diff = 0v rclk+ (differential) t rcih v diff = 0v t rcil fig1. differential clkin t rcip
THC63LVD1024_rev.2.4_e copyright?2012 thine electronics, inc. 7/23 thine electronics, inc. electrical characteristics cmos/ttl dc specifications v cc =vcc=pvcc=lvcc lvds receiver dc specifications v cc =vcc=pvcc=lvcc symbol parameter conditions min. typ max units v ih high level input voltage /pdwn, mode[2:0] r/f, oe, map pin 2.0 v cc v v il low level input voltage gnd 0.8 v v ih3 high level input voltage 3-level inputs (dk pin) 0.8v cc v cc v v im3 middle level input voltage 0.6v cc 0.4v cc v v il3 low level input voltage gnd 0.2v cc v v oh high level output voltage i oh = -8ma 2.4 v v ol low level output voltage i ol = 8ma 0.4 v i il input leakage current /pdwn, mode[2:0] r/f, oe, map pin a i il3 3-level input leakage current 3-level inputs (dk pin) a symbol parameter conditions min. typ. max. units v th differential input high threshold v ic = 1.2v 100 mv v tl differential input low threshold v ic = 1.2v -100 mv i ild differential input leakage current v in = 2.4v / 0v 30 a 0v v in v cc ? ?
THC63LVD1024_rev.2.4_e copyright?2012 thine electronics, inc. 8/23 thine electronics, inc. electrical characte ristics (continued) supply current v cc =vcc=pvcc=lvcc symbol parameter condition typ. max. units i rccw receiver supply current (worst case pattern) fig2. clkout=65mhz cl=8pf mode<1:0>=hh single-in/single-out mode2=l 201 ma clkout=85mhz 248 ma clkout=135mhz 364 ma clkout=32.5mhz mode<1:0>=hl single-in/ dual-out 138 ma clkout=42.5mhz 164 ma clkout=67.5mhz 233 ma clkout=65mhz mode<1:0>=lh dual-in/single-out mode2=l ddr output off 146 ma clkout=85mhz 165 ma clkout=135mhz 210 ma clkout=150mhz 223 ma clkout=32.5mhz mode<1:0>=lh dual-in/single-out mode2=h ddr output on 147 ma clkout=42.5mhz 165 ma clkout=67.5mhz 205 ma clkout=75mhz 217 ma clkin=65mhz mode<1:0>=ll dual-in/dual-out 366 ma clkin=85mhz 453 ma clkin=135mhz 671 ma i rccs receiver power down supply current /pdwn = l 50 a clkout checker pattern fig2. test pattern rxn, gxn, bxn x = 1,2 n = 0~9 hsync,vsync de cont11,12 cont21,22
THC63LVD1024_rev.2.4_e copyright?2012 thine electronics, inc. 9/23 thine electronics, inc. electrical characteristics (continued) output load limitation output load is limited so that junction temperature is not over 125 calculating formula tj = ta + ja * p p = v cc * (i outdt + i outck + i core ) i outdt = 1/2 * f clk * v cc * c load * n i outck = f clk * v cc * c load tj : junction temperature ta : ambient temperature ja : package thermal resistance = 22 [ /w] i core : supply current except all output buffers = 520ma i outdt : supply current only output buffers of data output. (r1,g1,b1,r2 ,g2,b2,hsync,vsync,de,cont11,cont12,cont21,cont22) i outck : supply current only output buffer of clkout. f clk : clkout frequency n : 67 (number of data output pin) c c load limitation 8 9 10 11 12 13 14 15 100 105 110 115 120 125 130 135 frequency[mhz] output load[pf]
THC63LVD1024_rev.2.4_e copyright?2012 thine electronics, inc. 10/23 thine electronics, inc. switching characteristics v cc =vcc=pvcc=lvcc symbol parameter min. typ. max. units t rcp clkout period (fig4) 6.67 t 250 ns t rch clkout high time (fig4) ns t rcl clkout low time (fig4) ns t dout ttl data out period (fig5,6) 6.67 t 250 ns t rs ttl data setup to clkout(fig5,6) 0.45t dout -0.45 ns t rh ttl data hold to clkout(fig5,6) 0.45t dout -0.45 ns t tlh ttl low to high transition time (fig 3) 0.7 1.0 ns t thl ttl high to low transition time (fig 3) 0.7 1.0 ns t sk receiver skew margin (fig7) t rcip =65mhz -650 0 650 ps t rcip =85mhz -450 0 450 ps t rcip =108mhz -250 0 250 ps t rcip =135mhz -170 0 170 ps t rip1 input data position0 (fig7) -t sk 0 +t sk ns t rip0 input data position1 (fig7) ns t rip6 input data position2 (fig7) ns t rip5 input data position3 (fig7) ns t rip4 input data position4 (fig7) ns t rip3 input data position5 (fig7) ns t rip2 input data position6 (fig7) ns t rpll phase lock loop set (fig8) 10.0 ms t rcd rclk +/- to clk out delay (fig9) mode<1:0>=ll dk=l, 75mhz 89.7 94 ns t rcip clkin period (fig7) 7.4 125.0 ns t deint mode<1:0>=hl (single in/ dual out mode) only de input period (fig9-1) 4t rcip t rcip *(2n) n= integer ns t deh de input high time (fig9-1) 2t rcip ns t del de input low time (fig9-1) 2t rcip ns t 2 --- t 2 --- t rcip 7 ------------- -t sk ? t rcip 7 ------------- - t rcip 7 ------------- -t sk + 2 t rcip 7 ------------- -t sk ? 2 t rcip 7 ------------- - 2 t rcip 7 ------------- -t sk + 3 t rcip 7 ------------- -t sk ? 3 t rcip 7 ------------- - 3 t rcip 7 ------------- -t sk + 4 t rcip 7 ------------- -t sk ? 4 t rcip 7 ------------- - 4 t rcip 7 ------------- -t sk + 5 t rcip 7 ------------- -t sk ? 5 t rcip 7 ------------- - 5 t rcip 7 ------------- -t sk + 6 t rcip 7 ------------- -t sk ? 6 t rcip 7 ------------- - 6 t rcip 7 ------------- -t sk +
THC63LVD1024_rev.2.4_e copyright?2012 thine electronics, inc. 11/23 thine electronics, inc. v cc /2 v cc /2 v cc /2 clkout rxn, gxn, bxn x = 1,2 n = 0~9 v cc /2 v cc /2 t rcp clkout fig5. clkout position and setup/hold timing t rs t rh r/f=h r/f=l r/f=h r/f=l dk=m dk=l clkout dk=h r/f=h r/f=l 6 t dout 28 ------------------- - or 7 t dout 28 ------------------- - v cc /2 v cc /2 t dout hsync,vsync de cont11,12 cont21,22 6 t dout 28 ------------------- - or 7 t dout 28 ------------------- - ac timing diagrams v cc /2 v cc /2 v cc /2 t rcp t rch t rcl clkout v cc /2 fig4. clkout period and high/low time ttl output ttl output load 20% 80% 20% 80% t tlh t thl c l =8pf fig3. cmos/ttl output load and transition time
THC63LVD1024_rev.2.4_e copyright?2012 thine electronics, inc. 12/23 thine electronics, inc. ac timing diagrams (continued) v cc /2 v cc /2 v cc /2 clkout t rcp clkout fig6. clkout position and setup/hold timing for double edge output mode t rs t rh r/f=h r/f=l r/f=h r/f=l dk=m dk=l clkout dk=h r/f=h r/f=l 7 t dout 28 ------------------- - t rs t rh v cc /2 1st pixel data 2nd pixel data v cc /2 v cc /2 v cc /2 v cc /2 v cc /2 v cc /2 v cc /2 7 t dout 28 ------------------- - 7 t dout 28 ------------------- - 7 t dout 28 ------------------- - mode<1:0>=lh, mode2=h t dout t dout r1n, g1n, b1n n = 0~9 hsync,vsync de cont11,12 v diff = 0v v diff = 0v rclk+ t rip1 t rip0 t rip6 t rip5 t rip4 t rip3 t rip2 ryx6 ryx5 ryx4 ryx3 ryx2 ryx1 ryx0 ryx+/- (differential) next cycle previous cycle current cycle ryx3? ryx2? ryx1? ryx0? ryx6?? t rcip fig7. lvds input data position x=1,2 y= a, b, c, d, e
THC63LVD1024_rev.2.4_e copyright?2012 thine electronics, inc. 13/23 thine electronics, inc. ac timing diagrams (continued) v diff = 0v t rcd rclk+ clkout r/f=l note: 1) vdiff = (rclk+) - (rclk-) fig9. rclk +/- to clk out delay 2.0v v cc /2 t rpll rclk+/- /pdwn clkout fig8. pll lock loop set time rc1+ rclk+ fig9-1. single in / dual out mode rc1(de) input timing de t deint t deh t del de de de de de v cc /2 current data current data ryx+/- x=1,2 y= a, b, c, d, e r1n, g1n, b1n n = 0~9 hsync,vsync de cont11,12
THC63LVD1024_rev.2.4_e copyright?2012 thine electronics, inc. 14/23 thine electronics, inc. output data mapping table2. output color data naming rule table3. ttl/cmos output data mapping (single-out mode, mode0=h) xyz description x=r red color data x=g green color data x=b blue color data y= none single pixel y=o dual pixel 1st pixel data y=e 2nd pixel data z=0-9 bit number 0: lsb (least significant bit) 9: msb (most significant bit) data signals receiver output pin names 30-bit 24-bit 18-bit 30-bit 24-bit 18-bit r0 r10 r1 r11 r2 r0 r12 r12 r3 r1 r13 r13 r4 r2 r0 r14 r14 r14 r5 r3 r1 r15 r15 r15 r6 r4 r2 r16 r16 r16 r7 r5 r3 r17 r17 r17 r8 r6 r4 r18 r18 r18 r9 r7 r5 r19 r19 r19 g0 g10 g1 g11 g2 g0 g12 g12 g3 g1 g13 g13 g4 g2 g0 g14 g14 g14 g5 g3 g1 g15 g15 g15 g6 g4 g2 g16 g16 g16 g7 g5 g3 g17 g17 g17 g8 g6 g4 g18 g18 g18 g9 g7 g5 g19 g19 g19 b0 b10 b1 b11 b2 b0 b12 b12 b3 b1 b13 b13 b4 b2 b0 b14 b14 b14 b5 b3 b1 b15 b15 b15 b6 b4 b2 b16 b16 b16 b7 b5 b3 b17 b17 b17 b8 b6 b4 b18 b18 b18 b9 b7 b5 b19 b19 b19
THC63LVD1024_rev.2.4_e copyright?2012 thine electronics, inc. 15/23 thine electronics, inc. output data mapping (continued) table4. ttl/cmos output data mapping (dual-out mode, mode0=l) 1st pixel data 2nd pixel data data signals receiver output pin names data signals receiver output pin names 30-bit 24-bit 18-bit 30-bit 24-bit 18-bit 30-bit 24-bit 18-bit 30-bit 24-bit 18-bit re0 r10 ro0 r20 re1 r11 ro1 r22 re2 re0 r12 r12 ro2 ro0 r22 r22 re3 re1 r13 r13 ro3 ro1 r23 r23 re4 re2 re0 r14 r14 r14 ro4 ro2 ro0 r24 r24 r24 re5 re3 re1 r15 r15 r15 ro5 ro3 ro1 r25 r25 r25 re6 re4 re2 r16 r16 r16 ro6 ro4 ro2 r26 r26 r26 re7 re5 re3 r17 r17 r17 ro7 ro5 ro3 r27 r27 r27 re8 re6 re4 r18 r18 r18 ro8 ro6 ro4 r28 r28 r28 re9 re7 re5 r19 r19 r19 ro9 ro7 ro5 r29 r29 r29 ge0 g10 go0 g20 ge1 g11 go1 g22 ge2 ge0 g12 g12 go2 go0 g22 g22 ge3 ge1 g13 g13 go3 go1 g23 g23 ge4 ge2 ge0 g14 g14 g14 go4 go2 go0 g24 g24 g24 ge5 ge3 ge1 g15 g15 g15 go5 go3 go1 g25 g25 g25 ge6 ge4 ge2 g16 g16 g16 go6 go4 go2 g26 g26 g26 ge7 ge5 ge3 g17 g17 g17 go7 go5 go3 g27 g27 g27 ge8 ge6 ge4 g18 g18 g18 go8 go6 go4 g28 g28 g28 ge9 ge7 ge5 g19 g19 g19 go9 go7 go5 g29 g29 g29 be0 b10 bo0 b20 be1 b11 bo1 b22 be2 be0 b12 b12 bo2 bo0 b22 b22 be3 be1 b13 b13 bo3 bo1 b23 b23 be4 be2 be0 b14 b14 b14 bo4 bo2 bo0 b24 b24 b24 be5 be3 be1 b15 b15 b15 bo5 bo3 bo1 b25 b25 b25 be6 be4 be2 b16 b16 b16 bo6 bo4 bo2 b26 b26 b26 be7 be5 be3 b17 b17 b17 bo7 bo5 bo3 b27 b27 b27 be8 be6 be4 b18 b18 b18 bo8 bo6 bo4 b28 b28 b28 be9 be7 be5 b19 b19 b19 bo9 bo7 bo5 b29 b29 b29
THC63LVD1024_rev.2.4_e copyright?2012 thine electronics, inc. 16/23 thine electronics, inc. lvds input data mapping rx1+/- rclk+ previous cycle current cycle fig10. lvds inputs mapped to ttl data outputs x= a, b, c, d, e rx11(n-1) rx10(n-1) rx16(n) rx15(n) rx14(n) rx13(n) rx12(n) rx11(n) rx10(n) rx16(n+1) (2nd pixel data) (1st pixel data) rx1+/- rclk+ next cycle current cycle x= a, b, c, d, e rx11(n) rx10(n) rx16(n+1) rx15(n+1) rx14(n+1) rx13(n+1) rx12(n+1) rx11(n+1) rx10(n+1) rx16(n+2) (2nd pixel data) (1st pixel data) mode1= h (single-in mode) rx1+/- rclk+ previous cycle current cycle fig11. lvds inputs mapped to ttl data outputs mode1= l (dual-in mode) x= a, b, c, d, e rx11(n-1) rx10(n-1) rx16(n) rx15(n) rx14(n) rx13(n) rx12(n) rx11(n) rx10(n) rx16(n+1) rx21(n-1) rx20(n-1) rx26(n) rx25(n) rx24(n) rx23(n) rx22(n) rx21(n) rx20(n) rx26(n+1) rx2+/- x= a, b, c, d, e
THC63LVD1024_rev.2.4_e copyright?2012 thine electronics, inc. 17/23 thine electronics, inc. lvds input data mapping (continued) table5. lvds input data mapping (single-in/single-out, mode<1:0>=hh) lvds input data mapping mode1 (output pin name) mapping mode2 (output pin name) ra10 r14 r12 ra11 r15 r13 ra12 r16 r14 ra13 r17 r15 ra14 r18 r16 ra15 r19 r17 ra16 g14 g12 rb10 g15 g13 rb11 g16 g14 rb12 g17 g15 rb13 g18 g16 rb14 g19 g17 rb15 b14 b12 rb16 b15 b13 rc10 b16 b14 rc11 b17 b15 rc12 b18 b16 rc13 b19 b17 rc14 hsync hsync rc15 vsync vsync rc16 de de rd10 r12 r18 rd11 r13 r19 rd12 g12 g18 rd13 g13 g19 rd14 b12 b18 rd15 b13 b19 rd16 cont11 cont11 re10 r10 r10 re11 r11 r11 re12 g10 g10 re13 g11 g11 re14 b10 b10 re15 b11 b11 re16 cont12 cont12
THC63LVD1024_rev.2.4_e copyright?2012 thine electronics, inc. 18/23 thine electronics, inc. lvds input data mapping (continued) table6. lvds input data mapping (single-in/dual-out, mode<1:0>=hl) 1st pixel data 2nd pixel data lvds input data (1st pixel data) mapping mode1 (output pin name) mapping mode2 (input pin name) lvds input data (1st pixel data) mapping mode1 (output pin name) mapping mode2 (output pin name) ra10(n) r14 r12 ra10(n+1) r24 r22 ra11(n) r15 r13 ra11(n+1) r25 r23 ra12(n) r16 r14 ra12(n+1) r26 r24 ra13(n) r17 r15 ra13(n+1) r27 r25 ra14(n) r18 r16 ra14(n+1) r28 r26 ra15(n) r19 r17 ra15(n+1) r29 r27 ra16(n) g14 g12 ra16(n+1) g24 g22 rb10(n) g15 g13 rb10(n+1) g25 g23 rb11(n) g16 g14 rb11(n+1) g26 g24 rb12(n) g17 g15 rb12(n+1) g27 g25 rb13(n) g18 g16 rb13(n+1) g28 g26 rb14(n) g19 g17 rb14(n+1) g29 g27 rb15(n) b14 b12 rb15(n+1) b24 b22 rb16(n) b15 b13 rb16(n+1) b25 b23 rc10(n) b16 b14 rc10(n+1) b26 b24 rc11(n) b17 b15 rc11(n+1) b27 b25 rc12(n) b18 b16 rc12(n+1) b28 b26 rc13(n) b19 b17 rc13(n+1) b29 b27 rc14(n) hsync hsync rc14(n+1) hsync hsync rc15(n) vsync vsync rc15(n+1) vsync vsync rc16(n) de de rc16(n+1) de de rd10(n) r12 r18 rd10(n+1) r22 r28 rd11(n) r13 r19 rd11(n+1) r23 r29 rd12(n) g12 g18 rd12(n+1) g22 g28 rd13(n) g13 g19 rd13(n+1) g23 g29 rd14(n) b12 b18 rd14(n+1) b22 b28 rd15(n) b13 b19 rd15(n+1) b23 b29 rd16(n) cont11 cont11 rd1 6(n+1) cont21 cont21 re10(n) r10 r10 re10(n+1) r20 r20 re11(n) r11 r11 re11(n+1) r21 r21 re12(n) g10 g10 re12(n+1) g20 g20 re13(n) g11 g11 re13(n+1) g21 g21 re14(n) b10 b10 re14(n+1) b20 b20 re15(n) b11 b11 re15(n+1) b21 b21 re16(n) cont12 cont12 re16(n+1) cont22 cont22
THC63LVD1024_rev.2.4_e copyright?2012 thine electronics, inc. 19/23 thine electronics, inc. lvds input data mapping (continued) table7. lvds input data mapping (dual-in/s ingle-out ddr on or off, mode<1:0>=lh, mode2=h or l) 1st pixel data 2nd pixel data lvds input data (1st pixel data) mapping mode1 (output pin name) mapping mode2 (output pin name) lvds input data (2nd pixel data) mapping mode1 (output pin name) mapping mode2 (output pin name) ra10 r14(n) r12(n) ra20 r14(n+1) r12(n+1) ra11 r15(n) r13(n) ra21 r15(n+1) r13(n+1) ra12 r16(n) r14(n) ra22 r16(n+1) r14(n+1) ra13 r17(n) r15(n) ra23 r17(n+1) r15(n+1) ra14 r18(n) r16(n) ra24 r18(n+1) r16(n+1) ra15 r19(n) r17(n) ra25 r19(n+1) r17(n+1) ra16 g14(n) g12(n) ra26 g14(n+1) g12(n+1) rb10 g15(n) g13(n) rb20 g15(n+1) g13(n+1) rb11 g16(n) g14(n) rb 21 g16(n+1) g14(n+1) rb12 g17(n) g15(n) rb22 g17(n+1) g15(n+1) rb13 g18(n) g16(n) rb23 g18(n+1) g16(n+1) rb14 g19(n) g17(n) rb24 g19(n+1) g17(n+1) rb15 b14(n) b12(n) rb25 b14(n+1) b12(n+1) rb16 b15(n) b13(n) rb26 b15(n+1) b13(n+1) rc10 b16(n) b14(n) rc20 b16(n+1) b14(n+1) rc11 b17(n) b15(n) rc21 b17(n+1) b15(n+1) rc12 b18(n) b16(n) rc22 b18(n+1) b16(n+1) rc13 b19(n) b17(n) rc23 b19(n+1) b17(n+1) rc14 hsync(n) hsync(n) rc24 hsync(n+1) hsync(n+1) rc15 vsync(n) vsync(n) rc25 vsync(n+1) vsync(n+1) rc16 de(n) de(n) rc26 de(n+1) de(n+1) rd10 r12(n) r18(n) rd20 r12(n+1) r18(n+1) rd11 r13(n) r19(n) rd21 r13(n+1) r19(n+1) rd12 g12(n) g18(n) rd22 g12(n+1) g18(n+1) rd13 g13(n) g19(n) rd23 g13(n+1) g19(n+1) rd14 b12(n) b18(n) rd24 b12(n+1) b18(n+1) rd15 b13(n) b19(n) rd25 b13(n+1) b19(n+1) rd16 cont11(n) cont11(n) rd26 cont11(n+1) cont11(n+1) re10 r10(n) r10(n) re20 r10(n+1) r10(n+1) re11 r11(n) r11(n) re21 r11(n+1) r11(n+1) re12 g10(n) g10(n) re22 g10(n+1) g10(n+1) re13 g11(n) g11(n) re23 g11(n+1) g11(n+1) re14 b10(n) b10(n) re24 b10(n+1) b10(n+1) re15 b11(n) b11(n) re25 b11(n+1) b11(n+1) re16 cont12(n) cont12(n) re26 cont12(n+1) cont12(n+1)
THC63LVD1024_rev.2.4_e copyright?2012 thine electronics, inc. 20/23 thine electronics, inc. lvds input data mapping (continued) table8. lvds input data mapping (dual-in/dual-out, mode<1:0>=ll) 1st pixel data 2nd pixel data lvds input data (1st pixel data) mapping mode1 (output pin name) mapping mode2 (output pin name) lvds input data (2nd pixel data) mapping mode1 (output pin name) mapping mode2 (output pin name) ra10 r14 r12 ra20 r24 r22 ra11 r15 r13 ra21 r25 r23 ra12 r16 r14 ra22 r26 r24 ra13 r17 r15 ra23 r27 r25 ra14 r18 r16 ra24 r28 r26 ra15 r19 r17 ra25 r29 r27 ra16 g14 g12 ra26 g24 g22 rb10 g15 g13 rb20 g25 g23 rb11 g16 g14 rb21 g26 g24 rb12 g17 g15 rb22 g27 g25 rb13 g18 g16 rb23 g28 g26 rb14 g19 g17 rb24 g29 g27 rb15 b14 b12 rb25 b24 b22 rb16 b15 b13 rb26 b25 b23 rc10 b16 b14 rc20 b26 b24 rc11 b17 b15 rc21 b27 b25 rc12 b18 b16 rc22 b28 b26 rc13 b19 b17 rc23 b29 b27 rc14 hsync hsync rc24 n/a rc15 vsync vsync rc25 rc16 de de rc26 rd10 r12 r18 rd20 r22 r28 rd11 r13 r19 rd21 r23 r29 rd12 g12 g18 rd22 g22 g28 rd13 g13 g19 rd23 g23 g29 rd14 b12 b18 rd24 b22 b28 rd15 b13 b19 rd25 b23 b29 rd16 cont11 cont11 rd26 cont21 cont21 re10 r10 r10 re20 r20 r20 re11 r11 r11 re21 r21 r21 re12 g10 g10 re22 g20 g20 re13 g11 g11 re23 g21 g21 re14 b10 b10 re24 b20 b20 re15 b11 b11 re25 b21 b21 re16 cont12 cont12 re26 cont22 cont22
THC63LVD1024_rev.2.4_e copyright?2012 thine electronics, inc. 21/23 thine electronics, inc. note 1)power on sequence power on lvds-tx after THC63LVD1024. 2)cable connection and disconnection don't connect and disconnect the lvds cable, when the power is supplied to the system. 3)gnd connection connect the each gnd of the pcb which lvds-tx and th c63lvd1024 on it. it is better for emi reduction to place gnd cable as close to lvds cable as possible. 4)multi drop connection multi drop connection is not recommended. 5)asynchronous use asynchronous use such as following system is not recommended. . lvds-tx THC63LVD1024 THC63LVD1024 tclk+ tclk- THC63LVD1024 THC63LVD1024 clkout data data ic tclk+ tclk- tclk+ tclk- lvds-tx lvds-tx ic clkout data clkout data ! THC63LVD1024 THC63LVD1024 clkout data data ic tclk+ tclk- tclk+ tclk- ! ic
THC63LVD1024_rev.2.4_e copyright?2012 thine electronics, inc. 22/23 thine electronics, inc. package exposed pad is gnd and must be soldered to pcb. 0.08 m 22.00 bsc. 0.20 +0.07/-0.03 0.50 bsc. seating plane s s 0.10 0.09 0.20 1.00 ref 1.40 1.60 0.05 0.15 1.40 +/-0.05 0.25 gage plane 0.60 +/-0.15 0.08 0.20r 0.08 r min 0.20 min 1 36 37 72 73 108 109 144 top view 7.20 7.20 exposed pad bottom view 1 36 37 72 73 108 109 144 22.00 bsc. 20.00 bsc. 20.00 bsc. 1 pin index 0 7 11 13 11 13 unit mm THC63LVD1024
THC63LVD1024_rev.2.4_e copyright?2012 thine electronics, inc. 23/23 thine electronics, inc. notices and requests 1. the product specifications descri bed in this material are subjec t to change without prior notice. 2. the circuit diagrams described in this material are examples of the application which may not always apply to the customer's design. we are not responsible fo r possible errors and omissions in this material. please note if errors or omis sions should be found in th is material, we may not be able to correct them immediately. 3. this material contains our copy right, know- how or other proprietary. copying or disclosing to third parties the contents of this material without our prior permission is prohibited. 4. note that if infringement of any third part y's industrial ownership should occur by using this product, we will be exempted fr om the responsibility unless it di rectly relates to the production process or functions of the product. 5. this product is presumed to be used for gene ral electric equipment, not for the applications which require very high reliab ility (including medical equipmen t directly concerning people's life, aerospace equipment, or nuclear control e quipment). also, when using this product for the equipment concerned with the cont rol and safety of the transpor tation means, the traffic signal equipment, or various types of safety equipment, please do it after applying appropriate measures to the product. 6. despite our utmost efforts to im prove the quality and reliability of the product, faults will occur with a certain small probability, which is inevit able to a semi-conductor product. therefore, you are encouraged to have sufficie ntly redundant or error preventiv e design applie d to the use of the product so as not to have our produc t cause any social or public damage. 7. please note that this product is not designed to be radiation-proof. 8. customers are asked, if require d, to judge by themselves if th is product falls under the category of strategic goods under the foreign ex change and foreign trade control law. thine electronics, inc. e-mail: sales@thine.co.jp

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